Serial media independent interface with double data rate

Details Serial media independent interface with double data rate Serial media independent interface with double data rate

2006-05-09

2006-05-09

Pham, Chi (Department: 2667)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S503000, C370S512000, C375S354000

Reexamination Certificate

active

07042893

ABSTRACT:
An SMII interface circuit to communicate data synchronous with a clock signal having a rising edge and a falling edge. The interface circuit includes a transmit circuit that is responsive to the clock signal to generate a first transmit serial stream and a second transmit serial stream. A receive circuit, responsive to the clock signal, to generate a receive serial stream from two receive data streams. The receive serial stream having a operating frequency that is about twice the operating frequency of each of the two receive data streams. Transmit and receive ports corresponding to the transmit and receive circuits each include a single pin to communicate the serial transmit data and the receive serial stream.

REFERENCES:
patent: 6385208 (2002-05-01), Findlater et al.
patent: WO 01/17166 (2001-03-01), None
patent: WO 01/47188 (2001-06-01), None
Cisco Systems, “Serial-MII Specification,” Feb. 9, 2000, Revision 2.1, ENG-46080.

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