Register controlled delay locked loop with reduced delay...

Details Register controlled delay locked loop with reduced delay... Register controlled delay locked loop with reduced delay...

2006-08-29

2006-08-29

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S152000, C327S153000, C377S064000, C377S069000

Reexamination Certificate

active

07098712

ABSTRACT:
A register controlled delay locked loop includes a clock generation unit which receives an external clock signal for generating a source clock signal by buffering the external clock signal and for generating a delay monitoring clock signal and a reference clock signal by diving the source clock signal by a natural number; a delay line control unit which receives the reference clock signal and a feed-backed clock signal for generating a normal shift control signal and an acceleration shift control signal based on a result of a comparison between phases of the reference clock signal and the feed-backed clock signal; a delay line unit which receives the source clock signal for generating a delay locked clock signal by delaying the source clock signal according to a delay amount of the delay line unit determined by the normal shift control signal and the acceleration shift control signal; and a delay model unit for estimating a delay amount generated while the external clock signal is passed to a data output pin to generate the feed-backed clock signal, wherein an absolute delay amount based on the acceleration shift control signal is larger than that based on the normal shift control signal.

REFERENCES:
patent: 6194930 (2001-02-01), Matsuzaki et al.
patent: 6342796 (2002-01-01), Jung
patent: 6433597 (2002-08-01), Jung
patent: 6791381 (2004-09-01), Stubbs et al.
patent: 6828835 (2004-12-01), Cho
patent: 2003/0108139 (2003-06-01), Jung
patent: 2003/0184355 (2003-10-01), Lee

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