Frequency doubler circuit

Details Frequency doubler circuit Frequency doubler circuit

1976-07-22

1977-08-16

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 20, 328140, 307218, 307246, H03B 1914

Patent

active

040428346

ABSTRACT:
The frequency doubler includes circuits for charging and discharging a capacitor at a predetermined rate in response to each incoming cycle. First and second comparators are connected between the capacitor and the input of an OR gate. These comparators limit the magnitudes of the charged voltage and the discharged voltage of the capacitor. The OR gate responds to both comparators being off during a part of the rising portion of the capacitor waveform and during a part of the falling portion of the capacitor waveform by providing pulses having twice the repetition rate as the input pulses. An output circuit may be connected to the output terminal of the OR gate for converting the output signal of the OR gate into a further output signal comprised of current pulses having constant amplitude and duration.

REFERENCES:
patent: 3548317 (1970-12-01), Bordonaro
patent: 3743946 (1973-07-01), Gass et al.
patent: 3753012 (1973-08-01), Frederiksen et al.
patent: 3770327 (1973-11-01), Ruof
patent: 3808543 (1974-04-01), Mueller

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