Selective bypassing of a multi-port register file

Details Selective bypassing of a multi-port register file Selective bypassing of a multi-port register file

2006-05-23

2006-05-23

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S201000

Reexamination Certificate

active

07051186

ABSTRACT:
A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.

REFERENCES:
patent: 5471593 (1995-11-01), Branigin
patent: 5799163 (1998-08-01), Park et al.
patent: 6092184 (2000-07-01), Wechsler
patent: 6668316 (2003-12-01), Gorshtein et al.

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