High-speed interchip interface protocol

Details High-speed interchip interface protocol High-speed interchip interface protocol

2006-02-07

2006-02-07

Ngo, Ricky (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C710S011000, C710S104000

Reexamination Certificate

active

06996106

ABSTRACT:
A communication protocol provides high-speed transfers of parallel data between an origination end and a destination end. The protocol involves regularly transmitting data from the origination end to the destination end, including transmitting idle data from the origination end when the destination end is busy and during periods when no commands, data or statuses are pending. When the destination end is not busy, data is sent from the origination end to the destination end by: sequentially transferring read or write commands and, according to a write protocol, pending write data; and transmitting idle packets during periods when no commands are pending. When the origination end is not busy, data is sent from the destination end to the origination end by: sequentially transferring pending end-of-write statuses; sequentially transferring pending read data and read statuses packets according to a read protocol during periods when no end-of-write statuses are pending; and transmitting idle packets during periods when no read data or read status are pending.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6263385 (2001-07-01), Gulick et al.
patent: 6611891 (2003-08-01), Hewitt et al.
patent: 6748442 (2004-06-01), Keller
patent: 2003/0051058 (2003-03-01), Phong et al.
IBM Technical Disclosure Bulletin, Dec. 1991, US; NA9112355.

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