Software implementation of synchronous memory barriers

Details Software implementation of synchronous memory barriers Software implementation of synchronous memory barriers

2006-02-07

2006-02-07

Zhen, Wei Y. (Department: 2122)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

Reexamination Certificate

active

06996812

ABSTRACT:
Selectively emulating sequential consistency in software improves efficiency in a multiprocessing computing environment. A writing CPU uses a high priority inter-processor interrupt to force each CPU in the system to execute a memory barrier. This step invalidates old data in the system. Each CPU that has executed a memory barrier instruction registers completion and sends an indicator to a memory location to indicate completion of the memory barrier instruction. Prior to updating the data, the writing CPU must check the register to ensure completion of the memory barrier execution by each CPU. The register may be in the form of an array, a bitmask, or a combining tree, or a comparable structure. This step ensures that all invalidates are removed from the system and that deadlock between two competing CPUs is avoided. Following validation that each CPU has executed the memory barrier instruction, the writing CPU may update the pointer to the data structure.

REFERENCES:
patent: 5155832 (1992-10-01), Hunt
patent: 5442758 (1995-08-01), Slingwine et al.
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5608893 (1997-03-01), Slingwine et al.
patent: 5636363 (1997-06-01), Bourekas et al.
patent: 5727209 (1998-03-01), Slingwine et al.
patent: 5796996 (1998-08-01), Temma et al.
patent: 6055605 (2000-04-01), Sharma et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6088771 (2000-07-01), Steely, Jr. et al.
patent: 6131155 (2000-10-01), Alexander et al.
patent: 6219690 (2001-04-01), Slingwine et al.
Sites and Witek,“Alpha AXP Architecture Reference Manual”, Second Edition, Digital Press., 1995, pp. 5-1-5-27.

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