Method for making an 8-shaped storage node DRAM cell

Details Method for making an 8-shaped storage node DRAM cell Method for making an 8-shaped storage node DRAM cell

1998-11-09

2000-03-07

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438253, H01L 2120

Patent

active

060339667

ABSTRACT:
A method for manufacturing an 8-shaped bottom storage node. A dielectric layer and a polysilicon layer are deposited. A bit line contact and a storage node contact are formed through the dielectric layer and the polysilicon layer down to an access transistor. After formation of the bit line contact and the storage node contact, the polysilicon layer is removed leaving the first dielectric layer. A polysilicon layer is deposited over the dielectric layer and into the bit line contact and storage node contacts. This is followed by a deposition of a tungsten silicide layer and a second dielectric layer. These layers are then etched to form a bit line above the bit line contact. Sidewall spacers are formed on the sidewalls of the bit line. Another polysilicon layer is deposited into the storage node contacts and above the bit line. This polysilicon layer is patterned and etched in an 8 pattern. Oxide spacers are formed on the sidewalls of the etched polysilicon layer. Next, using the oxide spacers and oxide as a hard mask, the polysilicon layer is etched until the top of the bit line is reached. Finally, the oxide spacers are removed and an 8 shaped storage node is formed.

REFERENCES:
patent: 5444005 (1995-08-01), Kim et al.
patent: 5604146 (1997-02-01), Tseng
patent: 5710073 (1998-01-01), Jeng et al.
patent: 5712202 (1998-01-01), Liaw et al.

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