Semiconductor integrated device having reduced jitter and...

Details Semiconductor integrated device having reduced jitter and... Semiconductor integrated device having reduced jitter and...

2006-10-24

2006-10-24

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

07126392

ABSTRACT:
A structure is provided for significantly reducing the current excessively consumed for generating a high-speed clock signal necessary for signal processing, and significantly improve the jitter characteristics of the high-speed clock signal. The structure includes a reference-clock signal generation circuit, a time-base processing circuit, a PLL circuit, and a high-speed signal processing circuit. A low-speed reference-clock signal generated by the reference-clock signal generation circuit is provided to the PLL circuit. The PLL circuit generates a high-speed clock signal by multiplying the reference-clock signal by a factor of N. The factor N is at least 100. To reduce a jitter of the high-speed clock signal generated by the PLL circuit, a natural angular frequency ωn and a damping factor ζ that relate to the response characteristics of the system of the PLL circuit are set to range from 3 kHz to 10 kHz, and 0.01 or less, respectively.

REFERENCES:
patent: 6246294 (2001-06-01), Gai
patent: 6704892 (2004-03-01), Kurd et al.
Berlin, Howard M., “Design of Phase-Locked Loop Circuits, with Experiments (PLL no sekkei to jitsuyou kairo)”, 3 sheets and 1 sheet of partial translation.

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