Semiconductor memory device capable of erasing or writing...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185030, C365S185290

Reexamination Certificate

active

07046559

ABSTRACT:
There is disclosed a semiconductor memory device including a memory cell array containing a plurality of banks each having one or more blocks, a data erase circuit configured to erase data from selected blocks in banks at a unit of block, and an automatic multi-block erase circuit configured to enable a data read circuit configured to read data from memory cells provided in one bank, when data erase operation for all erase-object blocks in the one bank is completed, while continuing a data erasing operation of a next erase-object block included in another bank.

REFERENCES:
patent: 5748528 (1998-05-01), Campardo et al.
patent: 5894437 (1999-04-01), Chang et al.
patent: 6151657 (2000-11-01), Sun et al.
patent: 6377502 (2002-04-01), Honda et al.
patent: 6388919 (2002-05-01), Terasaki
patent: 6512693 (2003-01-01), Honda et al.
patent: 6604168 (2003-08-01), Ogawa
patent: 325795 (2001-11-01), None

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