Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2006-10-31
2006-10-31
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
Reexamination Certificate
active
07129591
ABSTRACT:
Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.
REFERENCES:
patent: 4783766 (1988-11-01), Samachisa et al.
patent: 5914510 (1999-06-01), Hieda
patent: 11-067894 (1999-03-01), None
patent: 11-354400 (1999-12-01), None
patent: 2002-134701 (2002-05-01), None
patent: 1020020056269 (2002-07-01), None
English language abstract of Japanese Publication No. 2002-134701.
English language abstract of Japanese Publication No. 11-354400.
English language abstract of Japanese Publication No. 11-067894.
English language abstract of Korean Publication No. 1020020056269.
Cho In-Wook
Kim Jin-Hee
Kim Myeong-Cheol
Kim Sang-Su
Kim Sung-Ho
Marger & Johnson & McCollom, P.C.
Vu Hung
LandOfFree
Semiconductor device having align key and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having align key and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having align key and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3614982