Patent
1994-04-22
1996-06-11
Harvey, Jack B.
H01J 1300
Patent
active
055264964
ABSTRACT:
A bus-based apparatus and method for synchronous priority arbitration between modules in a computer system. The modules in the system have priority codes selected from the set B(m,r) of bounded weight codes. Arbitration is completed in, at most, r units of time. The design of the system can be optimized for speed, logic per module, and/or the number of modules connected to any bus line. Both arbitration time and arbitration logic may be decreased by increasing the bus width. The number of modules can be increased indefinitely by increasing only bus-width, while keeping arbitration time and arbitration logic fixed. The arbitration bus is a wired-OR bus.
REFERENCES:
patent: 4974148 (1990-11-01), Matteson
patent: 5101482 (1992-03-01), Kipnis
patent: 5111424 (1992-05-01), Donaldson et al.
patent: 5121487 (1992-06-01), Bechtolsheim
patent: 5140680 (1992-08-01), Best
patent: 5142672 (1992-08-01), Johnson et al.
patent: 5195185 (1993-03-01), Marenin
patent: 5239651 (1993-08-01), Sodos
patent: 5241601 (1993-08-01), Naito et al.
patent: 5241628 (1993-08-01), Solari
patent: 5241632 (1993-08-01), O'Connell et al.
patent: 5241661 (1993-08-01), Concilio et al.
patent: 5303382 (1994-04-01), Bush et al.
patent: 5377332 (1994-09-01), Entwistle et al.
Shlomo Kipnis; Priority Arbitration with Busses; pp. 154-173, 1990.
Chung-Trans Xuong M.
Harvey Jack B.
The University of British Columbia
LandOfFree
Method and apparatus for priority arbitration among devices in a does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for priority arbitration among devices in a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for priority arbitration among devices in a will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-361417