Stress mitigation layer to reduce under bump stress...

Details Stress mitigation layer to reduce under bump stress... Stress mitigation layer to reduce under bump stress...

2006-07-04

2006-07-04

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S762000, C438S613000

Reexamination Certificate

active

07071554

ABSTRACT:
In some embodiments, the invention provides a stress mitigation layer that reduces stress in a layer of a microelectronic device that is below a conductive connection structure, such as a bump.

REFERENCES:
patent: 6614112 (2003-09-01), Uchida
patent: 6630736 (2003-10-01), Ignaut
patent: 6649515 (2003-11-01), Moon et al.
patent: 6774037 (2004-08-01), Hussein et al.
Valery M. Dubin et al., “Use of Conductive Electrolessly Deposited Etch Stop Layers, Liner Layers and Vi Plugs In Interconnected Structures”, U.S. Appl. No. 10/139,052, filed May 3, 2002.
Jun He et al., “Mechanically Robust Interconnect for Low-K Dielectric Material Using Post Treatment”, U.S. Appl. No. 10/253,723, filed Sep. 24, 2002.

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