Semiconductor memory device and portable electronic...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185200, C365S185190

Reexamination Certificate

active

07092295

ABSTRACT:
A semiconductor memory device includes a controller programming a nonvolatile memory cell by applying a first pulse so that a charge amount smaller than a target charge amount is accumulated in the nonvolatile memory cell, a second pulse train so that a second charge amount smaller than the target charge amount and larger than the first charge amount is accumulated in the nonvolatile memory cell, and a third pulse train so that a third charge amount falling within an allowable error range of the target charge amount is accumulated. The semiconductor memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and memory functional units formed on both sides of the gate electrode.

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patent: 5608669 (1997-03-01), Mi et al.
patent: 5838041 (1998-11-01), Sakagami et al.
patent: 5-81072 (1993-11-01), None
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patent: 9-116119 (1997-05-01), None
patent: 2001-156188 (2001-06-01), None
patent: 2001-156189 (2001-06-01), None
patent: 2001-230332 (2001-08-01), None
patent: 2002-190535 (2002-07-01), None

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