Method and apparatus for reducing latency in a digital...

Details Method and apparatus for reducing latency in a digital... Method and apparatus for reducing latency in a digital...

2006-09-12

2006-09-12

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S316000, C708S319000

Reexamination Certificate

active

07107301

ABSTRACT:
A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith. The processing circuitry is operatively configured to: (i) define a first subset of signal paths through the delay generation circuitry, the first subset including the zero delay signal path, and at least a second subset of signal paths through the delay generation circuitry, the second subset including one or more nonzero delay signal paths; (ii) remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path; and (iii) incorporate the idle delay with the processing circuitry.

REFERENCES:
patent: 4852035 (1989-07-01), Michener
patent: 5235647 (1993-08-01), Van de Kerkhof
patent: 5557632 (1996-09-01), Kaku et al.
patent: 6751277 (2004-06-01), Pesquet-Popescu

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