N+1 frequency divider counter and method therefor

Details N+1 frequency divider counter and method therefor N+1 frequency divider counter and method therefor

1995-04-28

1996-06-11

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377 56, 377118, H03K 2108

Patent

active

055263917

ABSTRACT:
An N+1 frequency divider counter (20) has a binary counter (22), ones detect circuitry (26), control logic (24), and an output flip-flop (28). The binary counter (22) counts from an initial value to a final value for each half of an output clock signal. If N+1 is an even number, one full cycle is added to each half cycle of the output clock signal. If N+1 is an odd number, one-half of a cycle is added to each half phase of the output clock signal. At the final count value, the control logic (24) causes the output clock signal to transition on either the rising edge or the falling edge of an input clock signal. The N+1 counter (20) has a fifty percent duty cycle for all count values of N, and does not require additional circuitry to accommodate when N equals zero.

REFERENCES:
patent: 4443887 (1984-04-01), Shiramizu
patent: 4891825 (1990-01-01), Hansen
patent: 4935944 (1990-06-01), Everett
patent: 5127036 (1992-06-01), Pham
patent: 5365119 (1994-11-01), Kivari
patent: 5390223 (1995-02-01), Lindholm
patent: 5425074 (1995-06-01), Wong

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