Performance increase technique for use in a register file...

Details Performance increase technique for use in a register file... Performance increase technique for use in a register file...

2006-01-17

2006-01-17

Phung, Anh (Department: 2824)

Static information storage and retrieval

Plural shift register memory devices

C365S189011, C365S230030, C365S230050

Reexamination Certificate

active

06987686

ABSTRACT:
For increasing the performance of a register file that is constructed to include dual-Vtbitlines or single-Vtbitlines. A boost of the drive signal for one of the transistors of a bitline circuit, preferably for the high voltage threshold read-selection transistor of a local bitline (LBL) circuit. The drive signal amplitude is made greater than the normal supply voltage by some increment delta V.

REFERENCES:
patent: 6519204 (2003-02-01), Slamowitz et al.
“A Precise On-Chip Voltage Generator for a Gigascale DRAM with a Negative Word-Line Scheme”, Hitoshi Tanaka et al., IEEE Jurnal of Solid-State Circuits, vol. 34, No. 8, Aug. 1999, pp. 1084-1090.
A 130-nm 6-GHz 256 × 32 bit Leakage-Tolerant Register File, Ram K. Krishnamurthy, et al., IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, pp. 624-632.
“Session 10/Low-Power & Communication Signal Processing/Paper FA 10.3”, Tadahiro Kuroda et al.,.
“Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines”, Seongmoo Heo et al., IEEE Proceedings of the 29thAnnual International symposium on Computer Architecture, 2002, 11 pages.
“Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's”, Hiroshi Kawaguchi, et al., IEEE Symposium on VLSI Circuits Digest of Technical Papers, 1998, pp. 140-141.

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