Parity prediction for arithmetic increment function

Details Parity prediction for arithmetic increment function Parity prediction for arithmetic increment function

2006-01-24

2006-01-24

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S672000

Reexamination Certificate

active

06990507

ABSTRACT:
The present invention provides a method and apparatus to check the arithmetic increment function through prediction of the change in the bit-level parity of the result by means of a series of identical cells connected in a linear array. The array predicts the change in parity produced by the arithmetic increment function which allows the increment function to be checked in an efficient manner. The advantages of the present invention are that the parity check design saves hardware cost over prior schemes that require duplication of incrementers and comparison of the results and schemes that require generation of parity after incrementing, and that the iterative, identical cell implementation of the parity predictor is well-suited for current VLSI and future digital logic circuits as they progress towards molecular, self-assembling components.

REFERENCES:
patent: 3555255 (1971-01-01), Toy
patent: 3699322 (1972-10-01), Dorr
patent: 3732407 (1973-05-01), Brewster et al.
patent: 4879675 (1989-11-01), Brodnax

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