Fishing – trapping – and vermin destroying
Patent
1995-06-06
1998-08-25
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437 44, 437191, H01L 218247
Patent
active
057982791
ABSTRACT:
A method comprising the steps of depositing a first and second polysilicon layer, separated by an oxide layer; selectively etching the second polysilicon layer to form first gate regions; forming first substrate regions in the substrate and laterally in relation to the first gate regions; selectively etching the first polysilicon layer to form second gate regions of a length greater than the first gate regions; and forming in the substrate, laterally in relation to the second gate regions and partially overlapping the first substrate regions, second substrate regions of a higher doping level than the first substrate regions.
REFERENCES:
patent: 3984822 (1976-10-01), Simko et al.
patent: 4780431 (1988-10-01), Maggioni et al.
patent: 4808544 (1989-02-01), Matsui
patent: 4997777 (1991-03-01), Boivin
patent: 5034791 (1991-07-01), Kameyama et al.
patent: 5053849 (1991-10-01), Izawa
patent: 5104819 (1992-04-01), Freiberger et al.
patent: 5120668 (1992-06-01), Hsu et al.
patent: 5153144 (1992-10-01), Komori et al.
patent: 5175119 (1992-12-01), Matsutani
patent: 5200350 (1993-04-01), Gill et al.
patent: 5202277 (1993-04-01), Kameyama
patent: 5256584 (1993-10-01), Hartmann
patent: 5304504 (1994-04-01), Wei et al.
T. Huang et al., "A New LDD transistor with Inverse-T Gate Structure," IEEE Electron Device Letters, EDL-8(4):151-153, 1987.
D. Wen et al., "A Self-Aligned Inverse-T Gate Fully Overlapped LDD Device for Sub-Half Micron CMOS," International Electron Devices Meeting Technical Digest, 765-768, 1989.
J.E. Moon et al., IEEE Electron Device Letters, vol. 11, No. 5, pp. 221-223, "A New LDD Structure: Total Overlap With Polysilicon Spacer (TOPS),"May 1990.
Clementi Cesare
Crisenza Giuseppe
Carlson David V.
Chaudhari Chandra
Santarelli Bryan A.
SGS--Thomson Microelectronics S.r.l.
LandOfFree
Method of fabricating non-volatile memories with overlapping lay does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating non-volatile memories with overlapping lay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating non-volatile memories with overlapping lay will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-35910