Method of forming raised source/drain regions in an integrated c

Details Method of forming raised source/drain regions in an integrated c Method of forming raised source/drain regions in an integrated c

1996-07-22

1998-08-25

Wojciechowicz, Edward

Fishing, trapping, and vermin destroying

437 62, 437105, 437200, 437228, 437241, 257344, 257384, 257408, 257412, 257623, 257640, H01L 21265, H01L 2976

Patent

active

057982783

ABSTRACT:
A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Conductive raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.

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