Reduced jitter charge pumps and circuits and systems...

Details Reduced jitter charge pumps and circuits and systems... Reduced jitter charge pumps and circuits and systems...

2006-05-30

2006-05-30

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S148000, C327S111000

Reexamination Certificate

active

07053684

ABSTRACT:
A charge pump including a differential pair of transistors for controlling a current at a charge pump output node and a replica bias generator for selectively driving a first transistor of the differential pair of transistors into a fully-on state and a second transistor of the differential pair of transistors into a weak inversion state.

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Young, I.A., Greason, J.K., Smith, J.E., and Wong, K.L. “A PLL Clock Generator with 5 to 100 MHz Lock Range for Microprocessors” IEEE Journal of Solid-State Circuits. Nov. 1992, pp. 1599-1611, vol. 27, No. 11, Intel Corp., USA.

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