Method for forming thick copper self-aligned dual damascene

Details Method for forming thick copper self-aligned dual damascene Method for forming thick copper self-aligned dual damascene

2006-07-11

2006-07-11

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S509000, C438S691000, C438S710000

Reexamination Certificate

active

07074721

ABSTRACT:
A method for forming a void free ultra thick dual damascene copper feature providing a semiconductor process wafer comprising via openings formed in a first undoped silicate glass (USG) layer the first USG layer having an overlying a second USG layer formed having a thickness of greater than about 1 micron and an overlying silicon oxynitride BARC layer; forming a trench opening having a width of greater than about 1 micron to encompass one of the via openings; forming a barrier layer to line the dual damascene opening; forming a copper seed layer having a thickness of from about 1000 Angstroms to about 2000 Angstroms; carrying out a multi-step electrochemical deposition (ECD); and, carrying out a two step copper annealing process.

REFERENCES:
patent: 6368967 (2002-04-01), Besser
patent: 6566260 (2003-05-01), Chooi et al.
patent: 6686280 (2004-02-01), Shue et al.
patent: 6696760 (2004-02-01), Powers

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