Non-volatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185210, C365S185330

Reexamination Certificate

active

07016230

ABSTRACT:
A non-volatile semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a sense amplifier circuit for reading said memory cell array, wherein the sense amplifier circuit includes: a first transistor disposed between a bit line of the memory cell array and a sense node to serve for sensing bit line data, the first transistor being driven by a voltage generating circuit including a boost circuit to transfer a bit line voltage determined in response to data of a selected memory cell to the sense node; a second transistor coupled to the sense node for precharging the sense node prior to bit line data sensing; a data latch for judging a transferred bit line voltage level to store a sensed data therein; and a capacitor for boosting the sense node, one end thereof being connected to the sense node, the other end thereof being selectively driven by a boost-use voltage.

REFERENCES:
patent: 6140847 (2000-10-01), Le Campion
patent: 6373746 (2002-04-01), Takeuchi et al.
patent: 2002/0126531 (2002-09-01), Hosono et al.
patent: 2002/0171502 (2002-11-01), Partridge et al.
patent: 2003/0133338 (2003-07-01), Kanda et al.
patent: 2004/0109357 (2004-06-01), Cernea et al.
patent: 2005/0024939 (2005-02-01), Chen et al.
patent: 2001-167590 (2001-06-01), None

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