Drive circuit and power supply apparatus

Electric power conversion systems – Current conversion – Including d.c.-a.c.-d.c. converter

Reexamination Certificate

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C327S389000, C327S542000

Reexamination Certificate

active

07113412

ABSTRACT:
In charging a gate of a NMOS transistor Q1, the charging speed is adjustable by varying a resistor R1. When an inputted pulse signal VIN reverses to a negative voltage, a diode D2turns off. Then, current flows along a discharging loop formed by the gate capacitor, the resistor R1, the emitter of the transistor Q2, the base of the transistor Q2, the resistor R2and the capacitor C1, the transformer T1and the source of the NMOS transistor Q1. A reverse bias voltage is applied to the gate of the NMOS transistor Q1, thereby keeping the NMOS transistor Q1off-state stably.

REFERENCES:
patent: 4748351 (1988-05-01), Barzegar
patent: 5438294 (1995-08-01), Smith
patent: 5481219 (1996-01-01), Jacobs et al.
patent: 5699237 (1997-12-01), Seragnoli
patent: 6072702 (2000-06-01), Nakao et al.
patent: 08-149796 (1996-06-01), None
patent: 11-145810 (1999-05-01), None

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