Method of reference cell design for optimized memory circuit...

Details Method of reference cell design for optimized memory circuit... Method of reference cell design for optimized memory circuit...

2006-03-28

2006-03-28

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S210130

Reexamination Certificate

active

07020022

ABSTRACT:
A method for standard reference cell design is herein disclosed. The method includes determining a first number of individual bits to be employed in a standard reference cell design based on the number of individual bits that are included in core memory cells that are to be measured using the standard reference cell. The method further includes determining a range of variation in the core memory cells to be measured that is due to process variation in the generation of the core memory cells. In addition, the method includes determining an additional number of individual bits to be included in the standard reference cell design based on the determined range of variation. A standard reference cell that includes a number of individual bits equal to the sum of both the first and the additional number of individual bits is generated.

REFERENCES:
patent: 5737260 (1998-04-01), Takata et al.

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