Image-signal processing apparatus for clamping analog image...

Television – Image signal processing circuitry specific to television – A/d converters

Reexamination Certificate

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C348S573000

Reexamination Certificate

active

06989871

ABSTRACT:
An analog Y signal input from an input terminal101is clamped at a pedestal level in a clamp circuit102, and then, is converted to a digital image signal in a quantization circuit103. The pedestal level Dp of the digital output D(t)113is stored in a register702. A predetermined value Dref (Dref=0 for the Y signal) is subtracted from Dp in a subtracter802. The subtraction output806is subtracted from the digital output113in a subtracter803. The subtraction output805(D(t)−(Dp−Dref)) is a signal for which a shift caused by a variation in the precision of the clamp circuit102and the quantization circuit103has been compensated for. The subtraction output805is limited to a predetermined dynamic range by an overflow limiter circuit807, and output as Dout.

REFERENCES:
patent: 4651213 (1987-03-01), Takimoto
patent: 5008753 (1991-04-01), Kitaura et al.
patent: 5191422 (1993-03-01), Cho et al.
patent: 5200833 (1993-04-01), Suzuki
patent: 5339114 (1994-08-01), Lagoni et al.
patent: 5341218 (1994-08-01), Kaneko et al.
patent: 5708482 (1998-01-01), Takahashi et al.
patent: 6002445 (1999-12-01), Urayama

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