Programmable frequency dividing apparatus

Details Programmable frequency dividing apparatus Programmable frequency dividing apparatus

1991-08-13

1993-03-16

Sikes, William L.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

With programmable counter

377 47, 377 48, H03K 2138

Patent

active

051951118

ABSTRACT:
A programmable frequency dividing network comprises a plurality of cascade-connected programmable frequency dividing stages each of which divides the frequency of a clock pulse by two and three based on a logic level of a preset input signal used to change a variable division ratio from one to another. In addition, there is provided a gating means for determining or detecting whether or not each of the outputs of programmable frequency dividing stages of the programmable frequency dividing network after a programmable frequency dividing stage as a second stage is brought to a predetermined pattern and an instruction signal for making a decision as to the division of the division ratio by (+1) is inputted, so as to generate the output of a logic level for causing a programmable frequency dividing stage equivalent to a first stage to divide the frequency of the clock pulse by three if it is determined to be positive in the above detection process. Then, the output of the gating means is supplied to the programmable frequency dividing stage corresponding to the first stage in the programmable frequency dividing network so as to select either one of division ratios of n and (n+ 1) with respect to a programmable frequency dividing apparatus comprising the above network and the gating means.

REFERENCES:
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patent: 5077764 (1991-12-01), Yamashita
H. Futami et al., "A Single Chip 1.2 GHz PLL Frequency Synthesizer LSI", 1987, IEEE Int. Conf. on Consumer Electronics, New York, U.S., FIG. 2, pp. 194-195.
PLL, Thomas Schreiner, How to Product Any Frequency with Digital Synthesizers, ELO 1979, Franzis-Verlag GmbH, Munich, Germany.

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