Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-04-25
2006-04-25
Hjerpe, Richard (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S213000, C345S098000
Reexamination Certificate
active
07034796
ABSTRACT:
When count values CNT of a counter11are values other than 1, a selection signal SEL of a decode section18becomes “H”, so that a clock signal CLK is selected by a selection section17and it is inputted into the counter11and a shift section15as a display clock signal DCK. When the count value CNT becomes 1, the selection signal SEL becomes “L”, so that a clock signal CLK divided into ½ by a division section16is selected in the selection section17and outputted as the display clock signal DCK. Thereby, the count value CNT is maintained to be 1 for two cycles of the clock signal CLK. Thereby, the pulse width of a common signal C1outputted from the shift section15becomes two times the pulse width of the other common signals C2to C33. Therefore, large pixels driven on the basis of the common signal C1can be displayed with the same contrast.
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Hjerpe Richard
Pham Tammy
Wenderoth , Lind & Ponack, L.L.P.
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