Overerase correction in flash EEPROM memory

Details Overerase correction in flash EEPROM memory Overerase correction in flash EEPROM memory

2006-04-04

2006-04-04

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185300, C365S185330

Reexamination Certificate

active

07023734

ABSTRACT:
A method of overerase correction for memory cells in a memory array after the memory cells have been erased is provided comprising the following steps: (a) setting a gate voltage of memory cells from a first selected bit line exhibiting leakage current above a threshold value to an initial voltage level; (b) applying a series of overerase correction pulses to the first selected bit line during a selected time period; (c) detecting during the selected time period whether the bit line exhibits leakage current above the threshold value; (d) if the bit line exhibits leakage current above the threshold value after the selected time period, increasing the gate voltage and repeating steps (b) and (c); and (e) if it is detected that the bit line does not exhibit leakage current above the threshold value during the selected time period, selecting a second bit line and repeating steps (a) through (d).

REFERENCES:
patent: 5576991 (1996-11-01), Radjy et al.
patent: 5642311 (1997-06-01), Cleveland et al.
patent: 5822252 (1998-10-01), Lee et al.
patent: 6023426 (2000-02-01), Tang et al.
patent: 6046932 (2000-04-01), Bill et al.

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