Ramped soft programming for control of erase voltage...

Details Ramped soft programming for control of erase voltage... Ramped soft programming for control of erase voltage...

2006-03-28

2006-03-28

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185300

Reexamination Certificate

active

07020021

ABSTRACT:
A method of erasing bits in a multi-level cell flash memory array is described. The method includes applying over-erase verification after each erase pulse. If cells verify as over-erased, a ramped over-erase correction pulse is applied. The voltage of each over-erase correction pulse is incrementally greater than the previous pulse, until all bits in all cells pass the over-erase verification. In this way, the widths of the threshold voltage distributions of the erased bits are kept to a minimum.

REFERENCES:
patent: 6252803 (2001-06-01), Fastow et al.
patent: 6285588 (2001-09-01), Fastow
patent: 6515908 (2003-02-01), Miyawaki et al.

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