Method for dynamic balancing of a clock tree

Details Method for dynamic balancing of a clock tree Method for dynamic balancing of a clock tree

2006-05-09

2006-05-09

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S565000

Reexamination Certificate

active

07042269

ABSTRACT:
The present invention provides a method to balance a clock tree dynamically. A controllable buffer is inserted in a specific level of a clock tree, and a controller is provided for adjusting two clocks with different skew by controlling the PMOS/NMOS arrangements in the controllable buffer so as to generate more current for compensating the time delay of slow clock to a sink. This method effectively suppressed the clock skew generated by the voltage drop or the temperature variations in the synchronous logic circuit design.

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patent: 5774371 (1998-06-01), Kawakami
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patent: 6550045 (2003-04-01), Lu et al.
patent: 6653883 (2003-11-01), Schultz
patent: 6751786 (2004-06-01), Teng et al.
patent: 6763513 (2004-07-01), Chang et al.
patent: 6782519 (2004-08-01), Chang et al.
patent: 6897699 (2005-05-01), Nguyen et al.

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