Single-clock, strobeless signaling system

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S194000

Reexamination Certificate

active

06990042

ABSTRACT:
A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path.

REFERENCES:
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5376833 (1994-12-01), Chloupek
patent: 5489862 (1996-02-01), Risinger et al.
patent: 5498990 (1996-03-01), Leung et al.
patent: 5606717 (1997-02-01), Farmwald et al.
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5742798 (1998-04-01), Goldrian
patent: 5809263 (1998-09-01), Farmwald et al.
patent: 5812835 (1998-09-01), Ruuskanen
patent: 5831929 (1998-11-01), Manning
patent: 5838177 (1998-11-01), Keeth
patent: 5852378 (1998-12-01), Keeth
patent: 5852640 (1998-12-01), Kliza et al.
patent: 5860080 (1999-01-01), James et al.
patent: 5870347 (1999-02-01), Keeth et al.
patent: 5872736 (1999-02-01), Keeth
patent: 5910920 (1999-06-01), Keeth
patent: 5920518 (1999-07-01), Harrison et al.
patent: 5923611 (1999-07-01), Ryan
patent: 5926034 (1999-07-01), Seyyedy
patent: 5935263 (1999-08-01), Keeth et al.
patent: 5940608 (1999-08-01), Manning
patent: 5940609 (1999-08-01), Harrison
patent: 5946244 (1999-08-01), Manning
patent: 5946260 (1999-08-01), Manning
patent: 5949254 (1999-09-01), Keeth
patent: 5959929 (1999-09-01), Cowles et al.
patent: 5963502 (1999-10-01), Watanabe et al.
patent: 5986955 (1999-11-01), Siek et al.
patent: 5996043 (1999-11-01), Manning
patent: 6000022 (1999-12-01), Manning
patent: 6009487 (1999-12-01), Davis et al.
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6014759 (2000-01-01), Manning
patent: 6016282 (2000-01-01), Keeth
patent: 6026050 (2000-02-01), Baker et al.
patent: 6026051 (2000-02-01), Keeth et al.
patent: 6029250 (2000-02-01), Keeth
patent: 6029252 (2000-02-01), Manning
patent: 6031787 (2000-02-01), Jeddeloh
patent: 6031797 (2000-02-01), Van Ryzin et al.
patent: 6032220 (2000-02-01), Martin et al.
patent: 6032274 (2000-02-01), Manning
patent: 6034878 (2000-03-01), Osaka et al.
patent: 6047248 (2000-04-01), Georgious et al.
patent: 6094704 (2000-07-01), Martin et al.
patent: 6094727 (2000-07-01), Manning
patent: 6101197 (2000-08-01), Keeth et al.
patent: 6101612 (2000-08-01), Jeddeloh
patent: 6108795 (2000-08-01), Jeddeloh
patent: 6321282 (2001-11-01), Horowitz et al.
patent: 6462591 (2002-10-01), Garrett, Jr. et al.
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6724685 (2004-04-01), Braun et al.
patent: 6839393 (2005-01-01), Sidiropoulos
patent: 2000035831 (2000-02-01), None
patent: 2000307421 (2000-09-01), None
patent: WO 01/29680 (2001-04-01), None
Yeon et al., “A 2 5V 333Mb/s//pin 1Gh Double Data Rate SDRAM”, ISSCC Digest of Technical Papers, pp. 412-413, Feb. 17, 1999.
Peter Gillingham & Bill Vogley, “SLDRAM: High Performance Open-Standard Memory,” IEEE Micro, Nov./Dec. 1997, pp. 29-39, vol. 17, No. 6, Institute of Electrical and Electronics Engineers, Inc., Los Alamitos, California.
SLDRAM Inc., “SLD4M28DR400 4 MEG×18 SLDRAM: 400 Mb/s/pin SLDRAM 4 M×18 SLDRAM Pipelined, Eight Bank, 2.5 V Operation,” Jul. 9, 1998, pp. 1-69, SLDRAM, Inc., San Jose, California.
SLDRAM Consortium, 400 Mb/s/pin SLDRAM, 1997 Draft/Advance Data Sheet (pp. 1-59).
Song et al., “NRZ Timing Recovery Technique for Band-Limited Channels,” IEEE Journal of Solid-State Circuites, vol. 32, No. 4, pp. 514-520, (Apr. 1997).
Chang et al., “A 2Gb/s/pin CMOS Asymmetric serial Link,” Computer Science Laboratory, Stanford University.
Dally and Poulton, “Digital System Engineering,” (1998), pp. 361-366.
Intel, “440BX AGPset: 82443BX Host Bridge/Controller Datasheet,” (Apr. 1998).
Poulton, John, Signaling in High-Performance Memory System, ISSCC 1999.
Designline, (Micron Technology Inc.) vol. 8, Issue 3 3Z99 (pp. 1-24).

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