Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-04-18
2006-04-18
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185280, C365S185220
Reexamination Certificate
active
07031194
ABSTRACT:
A nonvolatile semiconductor memory that reduces disturbing voltage to a non-selected memory cell during a write operation. The nonvolatile semiconductor memory according to exemplary embodiments of the present invention include a memory cell array, a word line control circuit, and a line control circuit. The memory cell array includes a plurality of memory cells provided in matrix form, a plurality of word lines, a plurality of bit lines, and a plurality of source lines. The word line control circuit controls the plurality of word lines. The line control circuit controls the plurality of bit lines and the plurality of source lines. Each of the memory cells includes a gate electrode coupled to the word lines, a first impurity region, a second impurity region, and an electron trap region provided in between the gate electrode and a substrate. The electron trap region is provided at least on the first impurity region side of the first impurity region side and the second impurity region side. During a write operation in a selected memory cell, the word line control circuit supplies a selection voltage to a selected word line coupled to the selected memory cell, and also supplies an erase-error preventing voltage to a non-selected word line.
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Nguyen Tuan T.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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