Method and system for converting interlaced formatted video...

Television – Format conversion – Line doublers type

Reexamination Certificate

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Details

C348S459000

Reexamination Certificate

active

07113221

ABSTRACT:
Aspects of the invention include a 3:2 pull down detector coupled to a 3:2 cadence processor and a color edge detector coupled to a binder. The binder may be coupled to a 3:2 cadence processor. A filter, which may be a temporal or infinite impulse response filter, may be coupled to the binder. A selector may also be coupled to the 3:2 cadence processor. A memory and a processor may also be coupled to any of the 3:2 pull down detector, the 3:2 cadence processor, the color edge detector, the binder, the filter and said output selector. The selector may select between a filtered deinterlaced output and a reverse 3:2 pull down output.

REFERENCES:
patent: 6396543 (2002-05-01), Shin et al.
patent: 6891571 (2005-05-01), Shin et al.

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