Method for translating instructions in a speculative...

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

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Details

C703S026000, C703S027000, C712S228000, C712S209000, C712S227000

Reexamination Certificate

active

06990658

ABSTRACT:
A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

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patent: 2002/0124160 (2002-09-01), Johnson
Sites, Richard L. et al. “Binary Translation”, Communications of the ACM, Feb. 1993, vol. 36, No. 2, pp. 69-81.
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Alberto Ferreira De Souza and Peter Rounce, DYNAMICALLY SCHEDULING THE TRACE PRODUCED DURING PROGRAM EXECUTION INTO VLIW INSTRUCTIONS, Apr. 12, 1999, Proceedings of the 13thInternational Parallel Processing Symposium 10thSymposium on Parallel and Distributed Programming.
Alberto Ferreira De Souza, Home Page, retrieved Jan. 20, 2005, http://www.inf.ufes.br/alberto/papers/desouza_rounce99a.pdf)>.

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