Electrical computers and digital processing systems: processing – Processing architecture – Long instruction word
Reexamination Certificate
2006-07-18
2006-07-18
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Long instruction word
C709S247000, C712S210000
Reexamination Certificate
active
07080235
ABSTRACT:
A method for controlling functional units in a processor, according to which in a configuration a sequence of primary instruction words which consists of several instruction word parts and originates from a translation of a program code is compressed and stored as a sequence of associated program words. The invention also relates to a processor system for carrying out this method. The aim of the invention is to increase operating speed in an application-specific manner while retaining a low program word width. To this end, as regards the method, a program word contains a first characteristic of a primary instruction word and instruction word parts which differentiate the primary instruction word belonging to the program word from the primary instruction word belonging to the characteristic. By means of the first characteristic contained in the program word a secondary instruction word is generated by exchanging the instruction word parts contained in the program word with those in a preceding secondary instruction word. On the system side the aim of the invention is solved by providing for the instruction word buffer to consists of a memory with optional line-by-line access.
REFERENCES:
patent: 5253325 (1993-10-01), Clark
patent: 5636352 (1997-06-01), Bealkowski et al.
patent: 5652878 (1997-07-01), Craft
patent: 5819058 (1998-10-01), Miller et al.
patent: 6704859 (2004-03-01), Jacobs et al.
Smith, M.E. Gonzalez, and Storer, J.A. Parallel algorithms for data compression. Journal of the ACM. Vol. 32, Issue 2 (Apr. 1985). pp. 344-373.
Weiss et al., “Dynamic Codewith Reduction for VLIW Instruction Set Architectures in Digital Signal Processors”, Nov. 1996.
Lefurgy et al., “Improving Code Density Using Compression Techniques”, Dec. 1997.
Baker & Botts LLP
Rizzuto Kevin P.
Systemonic AG
Tejwani Manu J.
LandOfFree
Device and method for generating and executing compressed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device and method for generating and executing compressed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device and method for generating and executing compressed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3537824