Method of making a semiconductor package device that...

Details Method of making a semiconductor package device that... Method of making a semiconductor package device that...

2006-01-24

2006-01-24

Zarneke, David A. (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

Reexamination Certificate

active

06989295

ABSTRACT:
A method of making a semiconductor package device includes providing a conductive trace that includes a terminal and a lead, wherein the terminal and the lead are electrically connected to one another, attaching the conductive trace to a semiconductor chip using an insulative adhesive, wherein the chip includes a conductive pad, forming a first insulative housing portion that contacts the chip and the lead without contacting the terminal, wherein the lead protrudes laterally from and extends through the first insulative housing portion, forming a connection joint that contacts and electrically connects the conductive trace and the pad, and forming a second insulative housing portion that contacts the adhesive, the terminal and the first insulative housing portion after forming the first insulative housing portion, wherein the terminal protrudes downwardly from and extends through the second insulative housing portion, and the first and second insulative housing portions form an insulative housing that surrounds the chip.

REFERENCES:
patent: 3627901 (1971-12-01), Happ
patent: 3678385 (1972-07-01), Bruner
patent: 3930114 (1975-12-01), Hodge
patent: 4506238 (1985-03-01), Endoh et al.
patent: 4971930 (1990-11-01), Fusaroli et al.
patent: 5081520 (1992-01-01), Yoshii et al.
patent: 5149958 (1992-09-01), Hallenbeck et al.
patent: 5157480 (1992-10-01), McShane et al.
patent: 5207102 (1993-05-01), Takahashi et al.
patent: 5241133 (1993-08-01), Mullen, III et al.
patent: 5264714 (1993-11-01), Nakaya et al.
patent: 5394303 (1995-02-01), Yamaji
patent: 5405809 (1995-04-01), Nakamura et al.
patent: 5436500 (1995-07-01), Park et al.
patent: 5440231 (1995-08-01), Sugai
patent: 5530282 (1996-06-01), Tsuji
patent: 5665652 (1997-09-01), Shimizu
patent: 5674785 (1997-10-01), Akram et al.
patent: 5677566 (1997-10-01), King et al.
patent: 5744827 (1998-04-01), Jeong et al.
patent: 5744859 (1998-04-01), Ouchida
patent: 5804771 (1998-09-01), McMahon et al.
patent: 5811879 (1998-09-01), Akram
patent: 5834835 (1998-11-01), Maekawa
patent: 5834843 (1998-11-01), Mori et al.
patent: 5859471 (1999-01-01), Kuraishi et al.
patent: 5866939 (1999-02-01), Shin et al.
patent: 5893723 (1999-04-01), Yamanaka
patent: 5894107 (1999-04-01), Lee et al.
patent: 5949135 (1999-09-01), Washida et al.
patent: 5949655 (1999-09-01), Glenn
patent: 5951804 (1999-09-01), Kweon et al.
patent: 5973388 (1999-10-01), Chew et al.
patent: 6001671 (1999-12-01), Fjelstad
patent: 6013877 (2000-01-01), Degani et al.
patent: 6025650 (2000-02-01), Tsuji et al.
patent: 6114770 (2000-09-01), Akram et al.
patent: 6130116 (2000-10-01), Smith et al.
patent: 6143588 (2000-11-01), Glenn
patent: 6159770 (2000-12-01), Tetaka et al.
patent: 6198171 (2001-03-01), Huang et al.
patent: 6218728 (2001-04-01), Kimura
patent: 6232152 (2001-05-01), DiStefano et al.
patent: 6265770 (2001-07-01), Uchiyama
patent: 6274927 (2001-08-01), Glenn
patent: 6281568 (2001-08-01), Glenn et al.
patent: 6297543 (2001-10-01), Hong et al.
patent: 6303997 (2001-10-01), Lee
patent: 6326700 (2001-12-01), Bai et al.
patent: 6353265 (2002-03-01), Michii
patent: 6369595 (2002-04-01), Farnworth et al.
patent: 6445077 (2002-09-01), Choi et al.
patent: 6455356 (2002-09-01), Glenn et al.
patent: 6468836 (2002-10-01), DiStefano et al.
patent: 6512219 (2003-01-01), Webster et al.
patent: 57100761 (1982-06-01), None
patent: 01128897 (1989-05-01), None
patent: 06097352 (1994-04-01), None
Crowley, “Socket Developments for CSP and FBGA Packages,” Chip Scale Review, May 1998, pp. 37-40.
Forster, “Socket Challenges for Chip-Scale Packages, ” Chip Scale Review, May 1998, pp. 43-47.
Amagai, “Chip-Scale Packages for Center-Pad Memory Devices,” Chip Scale Review, May 1998, pp. 68-77.
Vandevelde et al., “The PSGA, a Lead-Free CSP for High Performance & High Reliable Packaging,” Proceedings of the 2001 International Symposium on Microelectronics, Oct. 9, 2001, pp. 260-265.
U.S. Appl. No. 09/865,367, filed May 24, 2001, entitled “Semiconductor Chip Assembly With Simultaneously Electroplated Contact Terminal and Connection Joint”.
U.S. Appl. No. 09/864,555, filed May 24, 2001, entitled “Semiconductor Chip Assembly with Simultaneously Electrolessly Plated Contact Terminal and Connection Joint”.
U.S. Appl. No. 09/864,773, filed May 24, 2001, entitled “Semiconductor Chip Assembly With Ball Bond Connection Joint”.
U.S. Appl. No. 09/878,649, filed Jun. 11, 2001, entitled “Method of Making a Semiconductor Chip Assembly with a Conductive Trace Subtractively Formed Before and After Chip Attachment”.
U.S. Appl. No. 09/878,626, filed Jun. 11, 2001, entitled “Method of Connecting a Conductive Trace to a Semiconductor Chip”.
U.S. Appl. No. 09/917,339, filed Jul. 27, 2001, entitled “Method of Connecting a Bumped Compliant Conductive Trace to a Semiconductor Chip”.
U.S. Appl. No. 09/927,216, filed Aug. 10, 2001, entitled “Semiconductor Chip Assembly with Hardened Connection Joint”.
U.S. Appl. No. 09/939,140, filed Aug. 24, 2001, entitled “Semiconductor Chip Assembly with Interlocked Conductive Trace”.
U.S. Appl. No. 09/962,754, filed Sep. 24, 2001, entitled “Method of Connecting a Conductive Trace and an Insulative Base to a Semiconductor Chip”.
U.S. Appl. No. 09/972,796, filed Oct. 6, 2001, entitled “Method of Connecting a Bumped Compliant Conductive Trace and an Insulative Base to a Semiconductor Chip”.
U.S. Appl. No. 09/997,973, filed Nov. 29, 2001, entitled “Method of Connecting a Bumped Conductive Trace to a Semiconductor Chip”.

Affiliated with

Also associated with

Rating

Method of making a semiconductor package device that... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making a semiconductor package device that..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a semiconductor package device that... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3536496