Method for programming dual bit memory devices to reduce...

Details Method for programming dual bit memory devices to reduce... Method for programming dual bit memory devices to reduce...

2006-07-18

2006-07-18

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185220

Reexamination Certificate

active

07079423

ABSTRACT:
The present invention provides a method for programming a selected bit in a memory cell of a non-volatile dual bit flash memory device. The method includes applying a positive voltage to a bit line associated with the selected bit and applying another positive voltage to a word line associated with the selected bit. Next, a positive voltage is applied to a second bit line associated with a complementary bit that shares the memory cell with the selected bit. A positive voltage is also applied to a third bit line that is adjacent to the second bit line and removed from the bit line associated with the selected bit by the second bit line. Applying a negative voltage to the word line then erases the complementary bit, but not its adjacent non-selected bit. The programming cycle is repeated until a desired threshold voltage is obtained.

REFERENCES:
patent: 6590811 (2003-07-01), Hamilton et al.
patent: 6934190 (2005-08-01), Liu et al.

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