Shift register, data-line driving circuit, and scan-line...

Details Shift register, data-line driving circuit, and scan-line... Shift register, data-line driving circuit, and scan-line...

2006-04-04

2006-04-04

Wu, Xiao (Department: 2674)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S209000, C345S090000, C345S096000

Reexamination Certificate

active

07023415

ABSTRACT:
The invention provides a shift register that reliably operates even when the driving ability of a clock signal is low. A data-line driving circuit includes a shift-register section, which has serially-connected shift-register unit circuits Ua1to Uan+2, and a clock-signal control section, which has serially-connected control unit circuits Uc1to Ucn+2. Each control unit circuit Uc1to Ucn+2 supplies an X clock-signal XCK and an inverted X clock-signal XCKB to the corresponding shift-register unit circuit Ua1to Uan+2 in a period of time when either one of signal voltages at nodes A1, A2, . . . at the prior and subsequent stages is active.

REFERENCES:
patent: 6232939 (2001-05-01), Saito et al.
patent: 6377235 (2002-04-01), Murade et al.
patent: 6515648 (2003-02-01), Tanaka et al.
patent: 6724363 (2004-04-01), Satoh et al.
patent: A-2002-259132 (2000-09-01), None
patent: 2000-322020 (2000-11-01), None
patent: A-2001-34236 (2001-02-01), None
patent: A-2001-324951 (2001-11-01), None

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