Multi-level logic input circuit

Details Multi-level logic input circuit Multi-level logic input circuit

1991-11-13

1993-03-16

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307454, 307451, 307361, H03K 1900, H03K 19094

Patent

active

051947668

ABSTRACT:
A multi-level logic input circuit is composed of a first and a second resistor, a first polarity current mirror circuit whose input is connected to the first resistor and which has a plurality of output nodes, and a second polarity current mirror circuit whose input is connected to the second resistor and which has a plurality of output nodes. The output nodes of the first polarity current mirror circuit are connected correspondingly with the output nodes of the second polarity current mirror circuit. The output nodes are led out as a plurality of output terminals. At least one of the output nodes of each of the current mirror circuits has a current ratio different from that in all the remaining output nodes thereof. The multi-level logic input circuit is simple in its configuration, and it enables to realize multi-level inputs with small current consumption.

REFERENCES:
patent: 3950656 (1976-04-01), Sumida et al.
patent: 3969633 (1976-07-01), Paluck et al.
patent: 4588908 (1986-05-01), Reich et al.
patent: 4591739 (1986-05-01), Nagano

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