Method for operating a memory cell array

Details Method for operating a memory cell array Method for operating a memory cell array

2006-09-26

2006-09-26

Phan, Trong (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280

Reexamination Certificate

active

07113428

ABSTRACT:
Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by Fowler-Nordheim tunneling, a lower potential for incipient programming of the memory cell is applied to the relevant word line (WLn) while the associated bit line (BLm) remains at the basic potential. What is thereby achieved is that a gate disturb occurring during the programming operation does not lead to erratic bits along the affected word line (WLn).

REFERENCES:
patent: 6195292 (2001-02-01), Usuki et al.
patent: 6272050 (2001-08-01), Cunningham et al.
patent: 6392929 (2002-05-01), Kim et al.
patent: 6639835 (2003-10-01), Forbes

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