Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
2006-05-02
2006-05-02
Khatri, Anil (Department: 2124)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S157000, C717S127000
Reexamination Certificate
active
07039909
ABSTRACT:
A method and apparatus for providing compiler transformation of code using regions with simplified data and control flow and value specialization are described. In one embodiment, the method includes identifying in the code a plurality of potential candidates for value specialization, selecting a group of candidates from the plurality of potential candidates based on a value profile associated with each potential candidate, and determining specialized data for each selected candidate using a corresponding value profile. The method further includes forming a plurality of optimized regions based on corresponding specialized data. Each optimized region includes one or more selected candidates.
REFERENCES:
patent: 5764885 (1998-06-01), Sites et al.
patent: 6170083 (2001-01-01), Adl-Tabatabai
patent: 6175948 (2001-01-01), Miller et al.
patent: 6377909 (2002-04-01), Ikegami
patent: 6487716 (2002-11-01), Choi et al.
patent: 6609248 (2003-08-01), Srivastava et al.
patent: 6779114 (2004-08-01), Chow et al.
patent: 2002/0170043 (2002-11-01), Bagley et al.
Chandra et al, “Physical type checking for C”, ACM PASTE, pp 66-75, Sep. 1999.
Zhai et al, “Compiler optimzation of memory resident value communication between speculative threads”, IEEE CGO, pp 1-12, Sep. 2004.
Xu et al, “Safety checking of machine code”, ACM PLDI, pp 70-82, 2000.
Auslander et al, “Fast effective dynamic compilation”, ACM PLDI, pp 149-159, May 1996.
Calder, B., et al., “Value Profiling and Optimization,” UCSD Technical Report, CS98-592, Jul. 1998, 15 pages.
Purser, Z, et al., “A Study of Slipstream Processors,” Proceeding of the Annual International Symposium on Microarchitecture, Dec. 10, 2000, pp. 269-280.
Gupta, R., et al., “Path Profile Guided Partial Dead Code Elimination Using Prediction,” Parallel Architectures and Compilation Techniques, Proceeding of the 1997 International Conference, pp. 102-113.
Calder, B., et al., “Value Profiling and Optimization,” UCSD Technical Report, CS98-592, Jul. 1998, 15 pages.
Chen, L., “FastForward: Aggressive Compiler Optimization with Speculative Multi-Threaded Support,” 6 pages.
Gupta, R., et al., “Path Profile Guided Partial Dead Code Elimination Using Prediction,” Parallel Architectures and Compilation Techniques, Proceeding of the 1997 International Conference, pp. 102-113.
Hwu, W., et al., “The Superblock: An Effective Technique for VLIW and Superscalar Compilation” The Journal of Supercomputing, Kluwer Academic Publishers, 1993 pp. 1-24.
Muth, R., et al., “Code Specialization Based On Value Profiles,” 20 pages.
Patel, S., “Improving Trace Cache Effectiveness With Branch Promotion And Trace Packing,” Proceedings of the 25thAnnual International Symposium on Computer Architecture, 1998, 10 pages.
Patel, S., “rePLay: A Hardware Framework For Dynamic Program Optimization,” CRCH Technical Report Draft, Dec. 1999, 26 pages.
Sundaramoorthy, K., et al., “Slipstream Processors: Improving Both Performance and Fault Tolerance,” ASPLOS 9thInternational Conference on Architectural Support For Programming Languages and Operating Systems, Cambridge, MA, U.S.A., Nov. 12-15, 2000, pp. 257-268.
Wu, Youfeng, et al., “Better Exploration of Region-Level Value Locality with Integrated Computation Reuse and Value Prediction,” Proceedings of the 28thInternational Symposium on Computer Architecture, Goteborg, Sweden, Jun. 30-Jul. 4, 2001, pp. 93-103.
Wu, Youfeng, et al., “Static Branch Frequency and Program Profile Analysis,” Proceedings of the 27thAnnual International Symposium on Microarchitecture, San Jose, CA, U.S.A. Nov. 30-Dec. 2, 1994, pp. 1-11.
PCT Search Report PCT/US02/27985 dated Jan. 5, 2004, 7 pages.
Purser, Z, et al., “A Study of Slipstream Processors,” Proceeding of the Annual International Symposium On Microarchitecture, Dec. 10, 2000, pp. 269-280.
Rotenberg, E., “Trace Processors,” Proceedings of the 30thAnnual International Symposium on Microarchitecture, Research Triangle Park, NC, U.S.A., Dec. 1-3, 1997, pp. 138-148.
Steffan, J., et al., “The Potential For Using Thread-Level Data Speculation to Facilitate Automatic Parallelization,” Proceedings 1998 4thInternational Symposium on High-Performance Computer Architecture, Las Vegas, NV, U.S.A., Feb. 1-4, 1998, pp. 2-13.
Chen Li-Ling
Wu Youfeng
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Khatri Anil
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