Digital delay locked loop and control method thereof

Details Digital delay locked loop and control method thereof Digital delay locked loop and control method thereof

2006-01-17

2006-01-17

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C327S161000

Reexamination Certificate

active

06987408

ABSTRACT:
There is provided a digital delay locked loop (DLL) which is capable of minimizing a jitter by predicting and detecting a maximum jitter timing. The digital delay locked loop includes: a clock generator for generating a source clock and a reference clock; a delay line provided with a plurality of unit delays, for delaying the source clock by a predetermined time; a delay model for reflecting a delay time of an actual internal circuit to an output of the delay line; a phase comparator for comparing a phase of the reference clock with a phase of a feedback clock outputted from the delay model; a jitter detector for detecting a maximum jitter timing in response to a phase comparison signal outputted from the phase comparator and generating a multi-delay enable signal; and a delay controller for controlling a delay amount of the delay line by unit-delay unit or multi-delay unit in response to the phase comparison signal and the multi-delay enable signal.

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