Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2006-04-04
2006-04-04
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S213000, C713S400000, C713S500000
Reexamination Certificate
active
07023442
ABSTRACT:
A video routing system including a plurality of video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series. Each video router in the linear series may successively operate on a digital video stream. Each video router provides a synchronous clock along with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. A common clock signal is distributed to each of the video routers. Each video router buffers the common clock signal to generate an output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream.
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Brightwell Mark K.
Chauhan Ulka J.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Singh Dalip K.
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