PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE...

Details PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE... PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE...

2005-12-13

2005-12-13

Vo, Ted T. (Department: 2192)

Data processing: software development, installation, and managem

Software program development tool

Testing or debugging

C712S227000

Reexamination Certificate

active

06976245

ABSTRACT:
When a branch instruction is decoded by the instruction decoders409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator411and the lower 3 bits are sent to the lower PC calculator405. The lower PC calculator405adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC404and sends the result to the lower PC404as the updated lower PC. The upper PC calculator411adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC403, and a carry that may be received from the lower PC calculator405, and sends the result to the upper PC403as the updated upper PC.

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Spohrer T., et al.: “Combination PC/Line Prefetch Address Adder” Motorola Technical Developments, Motorola Inc., vol. 13, Jul. 1, 1991, pp. 20-21.

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