Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2005-06-07
2005-06-07
Nguyen, Linh My (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S172000
Reexamination Certificate
active
06903585
ABSTRACT:
A pulse width modulated common mode feedback technique for a differential charge pump includes averaging the output of a differential charge pump to determine the common mode voltage; generating from the pump up and pump down pulses a set of up source pulses and down source pulses and a set of up sink pulses and down sink pulses and adjusting, in response to a difference between a reference voltage and the common mode voltage, the width of at least one of the sets of source and sink pulses to match the reference common mode voltages.
REFERENCES:
patent: 4156855 (1979-05-01), Crowley
patent: 6075406 (2000-06-01), Lee et al.
patent: 6111470 (2000-08-01), Dufour
patent: 6255873 (2001-07-01), Johnson et al.
Rhee, W., “Design of High-Performance CMOS Charge Pums in Phase-Locked Loops”, IEEE International Symposium on Circuits and Systems (ISCAS), 1999, vol. 2, pp. 545-548.
“An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump PLL's”, National Semiconductor Application Note 1001, Jul. 2001, pp. 1-8.
Byrd, et al.“A Fast Locking Scheme for PLL Frequency Synthesizers”, National Semiconductor Application Note 1000, Jul. 1995, pp. 1-6.
Curtin et al., “Phase Locked Loops for High-Frequency Receivers and Transmitters-Part 3”, Analog Dialogue 33-7 (1999), pp. 1-5.
Rhee et al., “A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order Delta Sigma Modulator”; IEEE Journal of Solid-State Circuits, vol. 35, No. 10, Oct. 2000, pp 1453-1460.
Greshlshchev et al., “SiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Applications”; IEEE Journal of Solid-State Circuits, vol. 35, No. 9, Sep. 2000, pp 1353-1359.
Bastos et al., “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC”; IEEE Journal of Solid-State Circuits, Vo. 33, No. 12, Dec. 1998, pp. 1959-1969.
Analog Devices Inc.
Iandiorio & Teska
Nguyen Linh My
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