Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
2005-06-14
2005-06-14
Harvey, Jack (Department: 2142)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000, C709S227000, C709S201000, C709S203000
Reexamination Certificate
active
06907474
ABSTRACT:
A system for adding multiple GPE blocks (in addition to the system/root GPE block device) to a computing system by creating a device entry in the ACPI namespace, and using a _CRS object to describe the system resources consumed by the device is described. The GPE block device may then access associated hardware devices through a well known mechanism (either I/O or Memory Mapped accesses). By creating additional GPE block devices within the ACPI namespace, general purpose events may be delivered using more traditional hardware interrupt mechanisms than with existing systems (e.g., wiring GPE blocks together). Moreover, by putting GPE block devices in the ACPI namespace, hardware components having hardware registers may be “hot plugged” to the computing system.
REFERENCES:
patent: 5475819 (1995-12-01), Miller et al.
patent: 5905890 (1999-05-01), Seaman et al.
patent: 5944780 (1999-08-01), Chase et al.
patent: 6256678 (2001-07-01), Traughber et al.
patent: 6446253 (2002-09-01), Mellmer
patent: 6546546 (2003-04-01), Van Doorn
patent: 6587909 (2003-07-01), Olarig et al.
patent: 6704785 (2004-03-01), Koo et al.
patent: 6711632 (2004-03-01), Chow et al.
patent: 6745203 (2004-06-01), Garg et al.
patent: 6748461 (2004-06-01), Oshins et al.
patent: 6754664 (2004-06-01), Bush
Snowflake: Spanning administrative domains—Howell, Kotz (1998); ftp.cs.dartmouth.edu/TR/TR98-343.ps.Z.
Security and Decentralized Control in the SFS Global File System—Mazières (1997) ; ftp.cag.lcs.mit.edu/dm/papers/mazieres:masters.ps.gz.
Q Instruction Set Architecture—John Watlington ; floe.www.media.mit.edu/projects/floe/isa/ISA.ps.Z.
Towards a Web Object Model; www.objs.com/OSA/wom.htm.
Intel Microsoft Toshiba,Advanced Configuration and Power Interface Specification, Feb. 2, 1999, Revision 1.0b, pp. 27, 98-100, and 115.
Gharachorloo et al., “Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors,”25 Years of International Symposia on Computer Architecture(Selected Papers),IEEE1990, pp. 376-387.
Chow et al., “The Priority-Based Coloring Approach to Register Allocation, ”acm Transactions on Programming Languages and Systems, vol. 12, No. 4, Oct. 1990, pp. 501-538.
Inouye et al., “Dynamic Network Reconfiguration Support for Mobile Computers,”Proceedings of the Third Annual ACM/IEEE International Conference on Mobile Computing and Networking, 1997, pp. 13-22.
Oshins Jacob
Pierce Tony D
Plante Stephane G.
Grace Ryan T.
Harvey Jack
Merchant & Gould
Microsoft Corporation
Vu Thong
LandOfFree
System and method for adding hardware registers to a power... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for adding hardware registers to a power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for adding hardware registers to a power... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3512501