Method of packaging electronic components with high reliability

Details Method of packaging electronic components with high reliability Method of packaging electronic components with high reliability

2005-08-16

2005-08-16

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S118000

Reexamination Certificate

active

06929973

ABSTRACT:
An electronic component that is provided with leads at a narrow pitch that are plated with solder is packaged by soldering the leads to lands on a printed circuit board on which the lands have been formed in a pattern of arrangement that corresponds to said leads. When packaging, solder paste is printed over areas on the lands that are greater in area than the area of the lands. The leads are then placed on this solder paste, and the solder paste is subjected to reflow to solder the leads onto the lands.

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patent: 5844249 (1998-12-01), Takano et al.
patent: 6296174 (2001-10-01), Chiang
patent: 8-64942 (1996-03-01), None
patent: 9-186445 (1997-07-01), None
Copy of European Search Report dated Apr. 20, 2004.
Vincent et al., GEC Journal of Research, vol. 11, No. 2, pp. 76-89 (1994).

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