Semiconductor integrated circuit and nonvolatile memory element

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185080

Reexamination Certificate

active

06906954

ABSTRACT:
0 Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM etc. Further, since the nonvolatile memory of high reliability can be formed without adding any step to a related art manufacturing process, such as a standard CMOS manufacturing process, the present invention may be readily applied to an LSI in which the nonvolatile memory and a logic LSI, or the nonvolatile memory and a DRAM are merged and packaged on an identical semiconductor substrate. Accordingly, a system LSI in which a flash memory is merged and packaged can be provided without increasing the cost of manufacture.

REFERENCES:
patent: 4040015 (1977-08-01), Fukuda
patent: 4279069 (1981-07-01), Beguwala et al.
patent: 5237530 (1993-08-01), Takashina et al.
patent: 5339279 (1994-08-01), Toms et al.
patent: 5694357 (1997-12-01), Mori
patent: 5828599 (1998-10-01), Herdt
patent: 5872994 (1999-02-01), Akiyama et al.
patent: 5937424 (1999-08-01), Leak et al.
patent: 5995409 (1999-11-01), Holland
patent: 5999069 (1999-12-01), Ushiroku
patent: 6026016 (2000-02-01), Gafken
patent: 6131139 (2000-10-01), Kikuchi et al.
patent: 6141256 (2000-10-01), Forbes
patent: 6181603 (2001-01-01), Jyouno et al.
patent: 6198663 (2001-03-01), Takizawa
patent: 6201733 (2001-03-01), Hiraki et al.
patent: 6229737 (2001-05-01), Walukas
patent: 263999 (1989-10-01), None
patent: 74392 (1992-03-01), None
patent: 127478 (1992-04-01), None
patent: 129091 (1992-04-01), None
patent: 163797 (1992-06-01), None
patent: 268180 (1994-09-01), None
Ohsaki et al., “A Single Ploy EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994.
1988 IEEE International Solid-State Circuits Conference Thursday, Feb. 18, 1988/ A30ns Fault Tolerant 16k CMOS EEPROM pp. 129-129.

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