Storage efficient minimization logic

Details Storage efficient minimization logic Storage efficient minimization logic

2005-08-16

2005-08-16

Le, Uyen (Department: 2163)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S200000

Reexamination Certificate

active

06931424

ABSTRACT:
A system is provided for finding the result of a binary operation performed on an array of values, along with its address, in a storage-efficient manner. The system is based on a binary tree structure having a pipeline of binary operators and corresponding multiplexers and storage elements to store the outputs of the multiplexers in addition to the partial addresses of the outputs represented by the outputs of the binary operators. Each computation stage adds one more bit of address until the address is completely known at the last computation stage. The invention reduces the amount of storage required for keeping track of the addresses that are the result of the binary operation.

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Daneshgaran et al, “Efficient parallel pipelinable VLSI architecture for finding the maximum binary number”, IEEE 1994, pp. 527-534.
Patent Abstracts of Japan, Abstract of Japanese Patent “SORT PROCESSOR”, Publication No. 04180124, Jun. 26, 1992, Japanese Application No. 02309365, Filed Nov. 15, 1990.

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