Method and apparatus for reducing write power consumption in...

Details Method and apparatus for reducing write power consumption in... Method and apparatus for reducing write power consumption in...

2005-08-23

2005-08-23

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S145000, C365S156000

Reexamination Certificate

active

06934213

ABSTRACT:
A method and circuit for reducing power consumption during write operations in a RAM are disclosed. In A RAM comprised of a plurality of memory cells, the bit lines that are coupled to each memory cell in the RAM and used to read and write data into the cell are coupled through charge share control circuitry to a charge sharing line. During write operations, the bit line that will receive a zero value is coupled to the charge share line before data is written to the cell. The charge sharing line equalizes the charge on the selected bit line and the charge share line and reduces the voltage differential that must be swung to write data into the cell.

REFERENCES:
patent: 4669062 (1987-05-01), Nakano
patent: 5808950 (1998-09-01), Suzuki
patent: 6512685 (2003-01-01), Lien et al.

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